DDR3 PCB设计时钟信号布线规则

参数定义信号组（Signal Group）Clock – CLK[5:0] and CLK#[5:0]拓扑(Topology)点到点差分对Differential Pair Point-to-point走线层表层（A）参考平面(Reference Plane)地平面差分信号阻抗（Differential Mode Impedance）80Ω+/-10%(80Ω)与非DDR3 信号的最小间距（Minimum Isolation Spacing to non-DDR3 Signals）25mil与其他DDR3 信号组的最小间距（Minimum Isolation Spacing to other-DDR3 Signal Groups）20mil封装长度的范围（P1, Package Length Range）731mil ~ 740mil 750mil ~ 759mil L1(Microstrip)(Fanout length segment)扇出差分对线宽/线距：4mil/4mil与其他DDR3 信号间距：4milL1 的长度应尽量短L2(Microstrip)与其他DDR3 信号间距：数据>20mil (trace-to-trace spacing > 4H)地址>20mil (trace-to-trace spacing > 4H)总的板级走线长度(Total Motherboard Length Limits, L1+L2)Max = 3000mil信号的总长度限制-P1+L1+L2Max = 4000mil最大的过孔数（Maximum Recommended Via Count）2 个，信号换层时在信号线附近增加电源或地的过孔SCK 与SCK#的长度匹配（SCK to SCK# Length Matching）(Total length including package)总长度的最大差别 < 5mil时钟对与时钟对的长度匹配（Clock-to-Clock Total Length Matching）到相同 DIMM 的总长度的最大差别：+/-10mil