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module CMBLOP (o, a, b, c);output o;input a, b, c;reg o;wire m = a | o;wire n = b | m;always @(c or n)o = c | n;endmodule在一般的数字设计中不用使用组合逻辑环,需要在其中进行插拍(异步设计除外)。 仿真竞争冒险:在两个或两个以上变量之间没有电路逻辑环,但有一个仿真反馈路径。module SIMLOP;wire a, c;reg b;always @ (a or c) beginb = a;endassign c = b;endmodulemodule wr_wr_race (clk, a, b); //Write – Write Raceinput clk,b;output a;wire d1, d2;reg c1, c2, a; always @(posedge clk) c1 = b;always @(posedge clk) c2 = ~b;assign d1 = c1;assign d2 = c2;always @(d1) a = d1;always @(d2) a = d2; endmoduleWrite-Write竞争冒险可以通过将写入操作合并成单个进程来解决。 Read - Write Contention Racealways @(posedge clk) /* write process */status_reg = new_val;always @(posedge clk) /* read process */status_output = status_reg;上述读写竞争冒险可以通过non-blocking赋值解决。 避免竞争冒险的几个建议:1.使用non blocking赋值。2.一个寄存器只在单个语句块中赋值。3.assign赋值语句仅用来连接,不用来产生逻辑。