毫不夸张！这款国外大佬的PCB布局一定让你看一眼就爱上！

前几天在AD官网看到一个非常好的PCB设计案例，一点不夸张！布局真的让人一眼就爱上。发布之后先后有四五个人问过我，其中不乏PCB专家级的老师也觉得很规范，很优美。抱着欣赏的态度，我把关键的PCB高清图整理了下来，为保持原汁原味，我把每一步的关键词都保留了原来英文的注解。以下供大家欣赏&&解压。

Image of the previous Pi.MX8 layout revision

Test-fitting the key components

Mechanical dimensions and connector locations of the PCB

Positioning of mounting holes and connectors on the PCB

Defining the antenna location

PCB with guard ring

Preliminary placement of the key components

Component placement top side

Component placement bottom side

Pi.MX8 Layerstack

Break-out routing on the top layer of the module

Trace width and spacing requirements for the i.MX8 break-out routing

Layerstack manager impedance profile differential 100 Ohm

Multiple net classes assigned to a design blanket

Impedance profile used in the design rule dialog–high priority rule overrides impedance profile

Design rooms in red shown underneath fine-pitch BGAs

Decoupling capacitors placed on bottom side of the LPDDR4 IC

DRAM routing bottom side

DRAM top side routing

DRAM L2 routing

Return path VIAs for the DRAM interface

Return path management - voids and splits on the left side, improved routing on the right side 

Layout planning in Inkscape with an Altium Designer screenshot as a background image

Top layer routing of the PiMX8 module

Routing inner signal layer 1

Routing inner signal layer 2

Multiplexer pinout with one long line in the interface

Bottom layer routing PiMX8 module

Available power plane layers

PMIC core and memory supply for the SoC

Voltage drop across power polygon

VCC_SOC polygon

VCC_ARM highlighted and DRAM power rail in purple

Power rails target impedance

Pin package delay in the schematic symbol

Pin delays in table format through the SCHLIB List toolbar

LPDDR4-4000 PCB delay tuning requirements

X-signal classes for the LPDDR4 tuning

Delay tuning documentation in Excel

Delay tuning address/command/control lines

Clock delay tuning top layer

LVDS routed to the multiplexer

MIPI-DSI routed to the multiplexer