RTL设计- 多时钟域按顺序复位释放

1 多时钟域的异步复位同步释放

当外部输入的复位信号只有一个，但是时钟域有多个时，使用每个时钟搭建自己的复位同步器即可，如下所示。

verilog代码如下：

module CLOCK_RESET( input rst_n, input aclk, input bclk, input cclk, output reg  arst_n, output reg  brst_n, output reg  crst_n );  reg arst_n0,arst_n1;reg brst_n0,brst_n1;reg crst_n0,crst_n1;  always @(posedge aclk or negedge rst_n)  if(rst_n==0) begin arst_n0<=1'b1; arst_n1<=1'b0; arst_n<=1'b0; end else begin arst_n<=arst_n1; arst_n1<=arst_n0; end  always @(posedge bclk or negedge rst_n)  if(rst_n==0) begin brst_n0<=1'b1; brst_n1<=1'b0; brst_n<=1'b0; end else begin brst_n<=brst_n1; brst_n1<=brst_n0; end   always @(posedge cclk or negedge rst_n)  if(rst_n==0) begin crst_n0<=1'b1; crst_n1<=1'b0; crst_n<=1'b0; end else begin crst_n<=crst_n1; crst_n1<=crst_n0; end   endmodule

RTL图如下：

2 多时钟域的按顺序复位释放

当多个时钟域之间对复位释放的时间有顺序要求时，将复位同步器级联起来就可以构成多个时钟域按顺序的复位释放（实际上就是延迟两拍）。

verilog代码：

module CLOCK_RESET( input rst_n, input aclk, input bclk, input cclk, output reg  arst_n, output reg  brst_n, output reg  crst_n );  reg arst_n0,arst_n1;reg brst_n0,brst_n1;reg crst_n0,crst_n1;  always @(posedge aclk or negedge rst_n)  if(rst_n==0) begin arst_n0<=1'b1; arst_n1<=1'b0; arst_n<=1'b0; end else begin arst_n<=arst_n1; arst_n1<=arst_n0; end  always @(posedge bclk or negedge rst_n)  if(rst_n==0) begin brst_n1<=1'b0; brst_n<=1'b0; end else begin brst_n<=brst_n1; brst_n1<=arst_n; end   always @(posedge cclk or negedge rst_n)  if(rst_n==0) begin crst_n1<=1'b0; crst_n<=1'b0; end else begin crst_n<=crst_n1; crst_n1<=brst_n; end   endmodule 

RTL图如下：