Icarus Verilog

2004年1月1日15:55

Icarus Verilog is a a GPLed Verilog compiler. Icarus Verilog includes a a parser that parses Verilog

(plus extensions) and generates an internal netlist. The netlist is passed to various processing steps

that transform the design to more optimal/practical forms, then passed to a code generator for final output.

The processing steps and the code generator are selected by command line switches.Icarus Verilog是免费的Verilog编译器，包含Verilog（plus extensions）语法分析器和产生内部网络表。命令行操作。

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