台积电采用GSS统计分析工具 提供精确设计分析思路

台积电采用GSS统计分析工具 提供精确设计分析思路0' title='台积电采用GSS统计分析工具 提供精确设计分析思路0' />

元器件交易网讯 11月13日消息，据外媒 Electronicsweekly报道，台积电宣布将采用Gold Standard Simulations(GSS)公司的统计分析工具，Gold Standard Simulations公司由格拉斯哥大学电气工程专业教授Asen Asenov创立。台积电此举标志着Gold Standard Simulations公司拿到无生产线晶圆制造领域的敲门砖。

Asen Asenov教授称：“我们首先需要做的是让无生产线晶圆制造厂接受这项技术，如若不然，制造厂商们也是无法接受的。如今，台积电采用了统计分析工具，我们可预见未来将会有更多无生产线晶圆制造厂商会采用它。”

GSS今年收获了一个丰收年。GSS统计分析工具是一款高级统计紧凑模型提取工具，可用以预测未来的设备性能和产量；可为台积电提供TCAD设备统计提取服务，同时另有一家不知名大公司同样采用了此款统计分析工具。

Asen Asenov教授表示：“明年，我们会更好！力争达到400万亿美元营收。GSS网站上大家都在热议关于英特尔 22 nm finfet制程技术，这加速催化了我们的订单；与此同时，此热议也为我们网站招致来每天数以千计的浏览数。”

GSS统计分析工具是一种先进的紧凑模型提取工具，是先进IC设计的必备工具，特别是在28 nm制程技术节点和链接方面，它有助于减少设计的悲观情绪和促进高西格玛产量分析和优化。同时它也能精确抓取先进设备数据用于精确设计分析，是CMOS集成电路设计中IC制造与技术之间必不可少的桥梁。(元器件交易网龙燕 译)

外媒原文：

TSMC is to use the statistical analysis tools of Gold Standard Simulations (GSS) founded and headed up by Professor Asen Asenov, professor of electrical engineering at Glasgow University.Adoption by TSMC is key to getting GSS’ technology accepted by the fabless community.

“The first thing was to get foundries to accept this technology,” Asenov tells Electronics Weekly, “ if the foundries don’t accept this then it’s difficult to get fabless companies to accept it. By having TSMC adopting this statistical abstraction technology we see significant reasons for fabless companies to adopt this technology too.”

GSS has had a good year. Besides the sale of its Mystic advanced statistical compact model extraction tool for TCAD device analysis to TSMC it has also had a sale to a large, unnamed semiconductor manufacturer. Sales this year will hit $1.3 million.

“Next year we’re aiming for $4 millioin,” says Asenov.

The catalyst for orders was a series of blogs on the GSS web-site about Intel’s 22nm finfet process. “Our blogs on Intel’s finfet technology resulted in people hitting on our web page in thousands a day,” says Asenov.

One of the capabilities of GSS’ statistical simulation tool is its ability to predict the performance and yield of future devices.

“People have been dealing with variability by putting extra margin in the design and this sacrifices performance in the silicon,” says Asenov, “technology has reached the stage where you can gain competitive advantage if you design better. At 28nm to get differentiation you need to do better design.”

“Statistical compact model extraction is an imperative in advanced IC design, particularly at the 28nm technology node and below, where it helps to reduce design pessimism and facilitates high-sigma yield analysis and optimization,” adds Asenov.

Everyone is looking for very high accuracy. The techniques for the GSS tools were based on tools developed by the financial industry to estimate yields from complicated financial instruments which can do very accurate analysis.

Mystic is an advanced compact model extraction tool, which has been specifically designed for accurate statistical compact model extraction. It provides a powerful yet flexible scripted environment that enables the development of robust yet accurate compact model extraction strategies for advanced devices based on data from TCAD simulations or silicon measurement.

Compact models are an essential bridge between IC manufacturing technology and IC design for CMOS devices, and must accurately capture the behaviour of advanced devices in order to enable accurate ‘right first time’ design.

Mystic simplifies the creation of the large, complex statistical compact model libraries required to manage the interplay between process-induced and purely statistical variability in advanced CMOS technologies.

The complex strategies and fitting algorithms needed to extract contemporary compact models require highly flexible extraction software. By utilising multiple back end simulators and GSS cluster computing and database technology, Mystic can tailor and customize statistical model extraction strategies for maximum accuracy in a highly application-specific environment.

Mystic is fully integrated with both GSS’ GARAND TCAD simulation tools and the RandomSPICE statistical circuit simulation engine. Fabless companies can adopt Mystic in their design flow.[!--empirenews.page--]

Asenov is a bit of a fan of ST’s FD-SOI technology. “At 14nm FD-SOI is much cheaper, 30-40% cheaper, than Intel’s technology,” says Asenov.

The problem for FD-SOI is getting an ecosystem together which will make it viable for users.

Asenov is on the board of Yorkshire IP developer SureCore which develops SRAM for FD-SOI.