基于FPGA的二值图像的边界提取算法的实现

基于FPGA的二值图像的边界提取算法的实现

1 背景知识

二值图像（Binary Image）是指将图像上的每一个像素只有两种可能的取值或灰度等级状态，人们经常用黑白、B&W、单色图像表示二值图像。二值图像是指在图像中，灰度等级只有两种，也就是说，图像中的任何像素不是0就是1，再无其他过渡的灰度值。

二值图像的边界提取主要基于黑白区域的边界查找。和许多边界查找算法相比它适合于二值图像。

图1 二值图像边界提取演示

如图1 所示，图1 a为一幅简单的二值图像，经过边界提取后形成如图1 b 所示的图像，显示出了白色区域的轮廓。

2 边界提取算法

使用黑色提取，背景为白色，‘1’表示白色，‘0’表示黑色。

图2 二值图像边界提取演示

我们使用3x3模板进行边界提取，所以当3x3九个点都是‘1’的时候，输出为‘1’，当九个点都是‘0’的时候，输出为‘1’，其他情况输出均为‘0’。

3 FPGA二值图像边界提取算法实现

图3二值图像膨胀FPGA模块架构

图3中我们使用串口传图传入的是二值图像。

FPGA源码：

Module name: boundary_extraction.v

Description: binary image boundary extraction

`timescale 1ns/1ps

module boundary_extraction(

input clk, //pixel clk

input rst_n,

input hs_in,

input vs_in,

input [15:0] data_in,

input data_in_en,

output hs_out,

output vs_out,

output reg [15:0] data_out,

output data_out_en

);

wire [15:0] line0;

wire [15:0] line1;

wire [15:0] line2;

reg [15:0] line0_data0;

reg [15:0] line0_data1;

reg [15:0] line0_data2;

reg [15:0] line1_data0;

reg [15:0] line1_data1;

reg [15:0] line1_data2;

reg [15:0] line2_data0;

reg [15:0] line2_data1;

reg [15:0] line2_data2;

reg data_out_en0;

reg data_out_en1;

reg data_out_en2;

reg hs_r0;

reg hs_r1;

reg hs_r2;

reg vs_r0;

reg vs_r1;

reg vs_r2;

wire[18:0] result_data;

line3x3 line3x3_inst(

.clken(data_in_en),

.clock(clk),

.shiftin(data_in),

.shiftout(),

.taps0x(line0),

.taps1x(line1),

.taps2x(line2)

);

//------------------------------------------------------------------------------

// Form an image matrix of three multiplied by three

//------------------------------------------------------------------------------

always @(posedge clk or negedge rst_n) begin

if(!rst_n) begin

line0_data0 <= 16'b0;

line0_data1 <= 16'b0;

line0_data2 <= 16'b0;

line1_data0 <= 16'b0;

line1_data1 <= 16'b0;

line1_data2 <= 16'b0;

line2_data0 <= 16'b0;

line2_data1 <= 16'b0;

line2_data2 <= 16'b0;

data_out_en0 <= 1'b0;

data_out_en1 <= 1'b0;

data_out_en2 <= 1'b0;

hs_r0 <= 1'b0;

hs_r1 <= 1'b0;

hs_r2 <= 1'b0;

vs_r0 <= 1'b0;

vs_r1 <= 1'b0;

vs_r2 <= 1'b0;

end

else if(data_in_en) begin

line0_data0 <= line0;

line0_data1 <= line0_data0;

line0_data2 <= line0_data1;

line1_data0 <= line1;

line1_data1 <= line1_data0;

line1_data2 <= line1_data1;

line2_data0 <= line2;

line2_data1 <= line2_data0;

line2_data2 <= line2_data1;

data_out_en0 <= data_in_en;

data_out_en1 <= data_out_en0;

data_out_en2 <= data_out_en1;

hs_r0 <= hs_in;

hs_r1 <= hs_r0;

hs_r2 <= hs_r1;

vs_r0 <= vs_in;

vs_r1 <= vs_r0;

vs_r2 <= vs_r1;

end

//-------------------------------------------------------------------

// line0_data0 line0_data1 line0_data2

// line1_data0 line1_data1 line1_data2

// line2_data0 line2_data1 line2_data2

//--------------------------------------------------------------------

always @(posedge clk or negedge rst_n) begin

if(!rst_n)

data_out <= 16'h0000;

else if(data_out_en1)

if((line0_data0 == 16'h0000) && (line0_data1 == 16'h0000) && (line0_data2 == 16'h0000) && (line1_data0 == 16'h0000) && (line1_data1 == 16'h0000) && (line1_data2 == 16'h0000) && (line2_data0 == 16'h0000) && (line2_data1 == 16'h0000) && (line2_data2 == 16'h0000))

data_out <= 16'hffff;

else if((line0_data0 == 16'hffff) && (line0_data1 == 16'hffff) && (line0_data2 == 16'hffff) && (line1_data0 == 16'hffff) && (line1_data1 == 16'hffff) && (line1_data2 == 16'hffff) && (line2_data0 == 16'hffff) && (line2_data1 == 16'hffff) && (line2_data2 == 16'hffff))

data_out <= 16'hffff;

else

data_out <= 16'h0000;

end

endmodule

4实验结果