实用低功耗CPLD设计

每个便携设备或者手持设备工程师都知道使功耗最小化是当前设计绝对需要的。但是，一个经验丰富的工程师就会明白微妙的细节可以使电池寿命延长到最大。这篇文章主要关注老练的专家怎样使用极低功耗的CPLD从嵌入式设计的I/O子系统里去挤出一点功耗。

我们先回顾一下CPLD在嵌入式设计中一般被用来减少功耗和版大小，以及BOM成本。接下来，我们看怎样在待机模式下减少CPLD功耗，不只是小心选择设备，而且是选择一个合适的总线结构。我们在工作状态下的节能探索将包括选择逻辑门技术，智能I/O设计技术及精确电压供电管理技术。

Any engineer involved with portable or handheld products knows that minimizing power
consumption is an absolute requirement for today’s designs. But only the veterans
understand the subtle yet important details that can stretch a systems’ battery life to the
maximum. In this article we’ll focus on how those seasoned experts use ultra-low-power
complex programmable logic devices (CPLDs) to wring out every last microwatt from
the I/O subsystems of their embedded designs.

We'll begin by reviewing how CPLDs are commonly used to shrink power, board space and BOM costs in embedded designs. Next, we'll see how to minimize a CPLD's power consumption in its standby mode, not only by carefully selecting the device itself but also by choosing an appropriate bus parking scheme. Our exploration of power conservation during active operation will include techniques such as selective logic gating, smart I/O design and precision supply voltage management.

详情请下载：lattice_practical_power.pdf