STM32 FSMC配置之SRAM

时间：2018-12-24 19:00:01

关键字： sram STM32 fsmc配置

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[导读]STM32的FSMC确实很方便，可以扩展诸如SRAM/NOR/NAND/PC Card/TFT等等，操作起来非常方便。关于FSMC参考《STM32参考手册》，上面非常详细。工程结构：user_sram.c//function of code:FSMC SRAM DriverSRAM chip#inclu

STM32的FSMC确实很方便，可以扩展诸如SRAM/NOR/NAND/PC Card/TFT等等，操作起来非常方便。关于FSMC参考《STM32参考手册》，上面非常详细。

工程结构：

user_sram.c

//function of code:FSMC SRAM DriverSRAM chip

#include"stm32f10x.h"
#include"user_sram.h"

void User_SRAM_Config(void)
{

FSMC_NORSRAMTimingInitTypeDefFSMC_NORSRAMTimingInitStructure;

FSMC_NORSRAMInitTypeDefFSMC_NORSRAMInitStructure;

GPIO_InitTypeDefGPIO_InitStructure;

RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC,ENABLE);

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD|
RCC_APB2Periph_GPIOE|
RCC_APB2Periph_GPIOF|
RCC_APB2Periph_GPIOG,ENABLE);

GPIO_InitStructure.GPIO_Pin=FSMC_SRAM_D0_Pin|FSMC_SRAM_D1_Pin|FSMC_SRAM_D2_Pin|
FSMC_SRAM_D3_Pin|FSMC_SRAM_D13_Pin|FSMC_SRAM_D14_Pin|
FSMC_SRAM_D15_Pin;
GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed=GPIO_Speed_50MHz;
GPIO_Init(FSMC_SRAM_D0_GPIO,&GPIO_InitStructure);

GPIO_InitStructure.GPIO_Pin=FSMC_SRAM_A16_Pin|FSMC_SRAM_A17_Pin|FSMC_SRAM_A18_Pin;
GPIO_Init(FSMC_SRAM_A16_GPIO,&GPIO_InitStructure);

GPIO_InitStructure.GPIO_Pin=FSMC_SRAM_NE3_Pin;
GPIO_Init(FSMC_SRAM_NE3_GPIO,&GPIO_InitStructure);

GPIO_InitStructure.GPIO_Pin=FSMC_SRAM_NWE_Pin|FSMC_SRAM_NOE_Pin;
GPIO_Init(FSMC_SRAM_NWE_GPIO,&GPIO_InitStructure);

GPIO_InitStructure.GPIO_Pin=FSMC_SRAM_NBL0_Pin|FSMC_SRAM_NBL1_Pin;
GPIO_Init(FSMC_SRAM_NBL0_GPIO,&GPIO_InitStructure);

FSMC_NORSRAMTimingInitStructure.FSMC_AddressSetupTime=0;
FSMC_NORSRAMTimingInitStructure.FSMC_AddressHoldTime=0;//复用IO用
FSMC_NORSRAMTimingInitStructure.FSMC_DataSetupTime=1;
FSMC_NORSRAMTimingInitStructure.FSMC_BusTurnAroundDuration=0;//总线恢复时间
FSMC_NORSRAMTimingInitStructure.FSMC_CLKDivision=0;//同步用
FSMC_NORSRAMTimingInitStructure.FSMC_DataLatency=0;//同步用数据产生时间产生第一个数据的时钟数目
FSMC_NORSRAMTimingInitStructure.FSMC_AccessMode=FSMC_AccessMode_A;//模式A

FSMC_NORSRAMInitStructure.FSMC_Bank=FSMC_Bank1_NORSRAM3;//FSMC模块: bank1 sram3
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux=FSMC_DataAddressMux_Disable;//数据地址复用:失能
FSMC_NORSRAMInitStructure.FSMC_MemoryType=FSMC_MemoryType_SRAM;//存储器类型:SRAM
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth=FSMC_MemoryDataWidth_16b;//数据宽度:8位
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode=FSMC_BurstAccessMode_Disable;//同步成组模式:失能
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait=FSMC_AsynchronousWait_Disable;//同步时间等待:失能
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity=FSMC_WaitSignalPolarity_Low;//等待信号极性:低电平同步模式才有效
FSMC_NORSRAMInitStructure.FSMC_WrapMode=FSMC_WrapMode_Disable;//Bank写模式:失能
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive=FSMC_WaitSignalActive_BeforeWaitState; //等待信号位置:Wait信号之前
FSMC_NORSRAMInitStructure.FSMC_WriteOperation=FSMC_WriteOperation_Enable;//写操作:使能
FSMC_NORSRAMInitStructure.FSMC_WaitSignal=FSMC_WaitSignal_Disable;//等待信号:失能只在突发模式有效
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode=FSMC_ExtendedMode_Disable;//扩展模式:失能
FSMC_NORSRAMInitStructure.FSMC_WriteBurst=FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct=&FSMC_NORSRAMTimingInitStructure;//读操作时序
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct=&FSMC_NORSRAMTimingInitStructure;//写操作时序

FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);

FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3,ENABLE);
}

void User_SRAM_WriteData(uint16_t *WriteData,uint32_t WriteAddress,uint32_t WriteNumberOfHalfWord)
{
for(;WriteNumberOfHalfWord!=0;WriteNumberOfHalfWord--)
{
*(uint16_t*)(FSMC_BANK1_SRAM3_Address+WriteAddress)= *WriteData++;
WriteAddress+=2;
}
}

void User_SRAM_ReadData(uint16_t *ReadData,uint32_t ReadAddress,uint32_t ReadNumberOfHalfWord)
{
for(;ReadNumberOfHalfWord!=0;ReadNumberOfHalfWord--)
{
*ReadData++=*(uint16_t*)(FSMC_BANK1_SRAM3_Address+ReadAddress);

ReadAddress+=2;
}
}

user_sram.h

//FSMC SRAM头文件

#ifndef _USER_SRAM_H
#define _USER_SRAM_H

#include"stm32f10x.h"

#defineFSMC_BANK1_SRAM3_Address((uint32_t)0x68000000)//0x60000000+(0x6fffffff-0x60000000)/4*2+1

#defineFSMC_SRAM_RCCRCC_AHBPeriph_FSMC

#defineFSMC_SRAM_D0_RCCRCC_APB2Periph_GPIOD
#defineFSMC_SRAM_D0_GPIOGPIOD
#defineFSMC_SRAM_D0_PinGPIO_Pin_14

#defineFSMC_SRAM_D1_RCCRCC_APB2Periph_GPIOD
#defineFSMC_SRAM_D1_GPIOGPIOD
#defineFSMC_SRAM_D1_PinGPIO_Pin_15

#defineFSMC_SRAM_D2_RCCRCC_APB2Periph_GPIOD
#defineFSMC_SRAM_D2_GPIOGPIOD
#defineFSMC_SRAM_D2_PinGPIO_Pin_0

#defineFSMC_SRAM_D3_RCCRCC_APB2Periph_GPIOD
#defineFSMC_SRAM_D3_GPIOGPIOD
#defineFSMC_SRAM_D3_PinGPIO_Pin_1

#defineFSMC_SRAM_D4_RCCRCC_APB2Periph_GPIOE
#defineFSMC_SRAM_D4_GPIOGPIOE
#defineFSMC_SRAM_D4_PinGPIO_Pin_7

#defineFSMC_SRAM_D5_RCCRCC_APB2Periph_GPIOE
#defineFSMC_SRAM_D5_GPIOGPIOE
#defineFSMC_SRAM_D5_PinGPIO_Pin_8

#defineFSMC_SRAM_D6_RCCRCC_APB2Periph_GPIOE
#defineFSMC_SRAM_D6_GPIOGPIOE
#defineFSMC_SRAM_D6_PinGPIO_Pin_9

#defineFSMC_SRAM_D7_RCCRCC_APB2Periph_GPIOE
#defineFSMC_SRAM_D7_GPIOGPIOE
#defineFSMC_SRAM_D7_PinGPIO_Pin_10

#defineFSMC_SRAM_D8_RCCRCC_APB2Periph_GPIOE
#defineFSMC_SRAM_D8_GPIOGPIOE
#defineFSMC_SRAM_D8_PinGPIO_Pin_11

#defineFSMC_SRAM_D9_RCCRCC_APB2Periph_GPIOE
#defineFSMC_SRAM_D9_GPIOGPIOE
#defineFSMC_SRAM_D9_PinGPIO_Pin_12

#defineFSMC_SRAM_D10_RCCRCC_APB2Periph_GPIOE
#defineFSMC_SRAM_D10_GPIOGPIOE
#defineFSMC_SRAM_D10_PinGPIO_Pin_13

#define FSMC_SRAM