中芯国际在65/45nm制程中采用Cadence的DFM方案
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中芯国际将采用Cadence Design Systems公司的“Litho Physical Analyzer”和“Litho Electrical Analyzer”作为65nm和45nm制程的设计工具。这两款工具可更好地模拟光刻工艺对器件制造的影响。
SMIC is to adopt Cadence Design Systems ‘Litho Physical Analyzer’ and ‘Litho Electrical Analyzer’ for IC designs entering into manufacturing for both the 65nm and 45nm nodes. Both tools enable better simulation of the impact of lithography processes on manufacturability of devices.
"The necessity to address physical and electrical variation at 65 and 45 nanometers requires a holistic approach that starts at the cell level and considers the entire context of the design," said Max Liu, VP of SMIC Design Services Center. "With the Cadence DFM flow, we could analyze cell and IP variability and accurately model their performance in real silicon. By characterizing and reducing the variability, our customers will be able to reduce guard-banding and to produce higher quality silicon. The solution also enables near-linear scalability, which is necessary for a full-chip electrical DFM verification flow."
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相关链接（英文）：
http://www.fabtech.org/news/_a/smic_selects_cadence_dfm_solution_for_65_45nm_production/
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