【MCU】16bit CPU设计实战(二)
时间：2021-11-11 14:10:41
[导读]本CPU设计基于16bitRISC指令集、哈佛结构完成，架构图如下：CPU架构A.MemoryAccessInstructions1.LoadWord: LDws,offset(rs1)ws:=Mem16[rs1offset]2.StoreWord: ...
本CPU设计基于16bit RISC指令集、哈佛结构完成，架构图如下：
CPU架构
A. Memory Access Instructions
1. Load Word:
LD ws, offset(rs1) ws:=Mem16[rs1 offset]
2. Store Word:
ST rs2, offset(rs1) Mem16[rs1 offset]=rs2
B. Data Processing Instructions
1. Add:
ADD ws, rs1, rs2 ws:=rs1 rs2
2. Subtract:
SUB ws, rs1, rs2 ws:=rs1 – rs2
3. Invert (1‘s complement):
INV ws, rs1 ws:=!rs1
4. Logical Shift Left:
LSL ws, rs1, rs2 ws:=rs1 << rs2
5. Logical Shift Right: LSR ws, rs1, rs2 ws:=rs1 >> rs2
6. Bitwise AND: AND ws, rs1, rs2 ws:=rs1 • rs2
7. Bitwise OR: OR ws, rs1, rs2 ws:=rs1 | rs2
8. Set on Less Than:
SLT ws, rs1, rs2 ws:=1 if rs1 < rs2; ws:=0 if rs1 ≥ rs2
C. Control Flow Instructions
1. Branch on Equal:
BEQ rs1, rs2, offset
Branch to (PC 2 (offset << 1)) when rs1 = rs2
2. Branch on Not Equal:
BNE rs1, rs2, offset
Branch to (PC 2 (offset << 1)) when rs1 != rs2
3. Jump: JMP offset Jump to {PC [15:13], (offset << 1)}
Instruction Format of the RISC
Processor Control Unit Design:
ALU Control Unit Design:Verilog code for the RISC processor:
1. Verilog code for Instruction Memory :
`include "Parameter.v"// fpga4student.com // FPGA projects, VHDL projects, Verilog projects // Verilog code for RISC Processor // Verilog code for Instruction Memorymodule Instruction_Memory( input[15:0] pc, output[15:0] instruction);
reg [`col - 1:0] memory [`row_i - 1:0]; wire [3 : 0] rom_addr = pc[4 : 1]; initial begin $readmemb("./test/test.prog", memory,0,14); end assign instruction = memory[rom_addr];
endmodule2. Verilog code for register file:
`timescale 1ns / 1ps// fpga4student.com // FPGA projects, VHDL projects, Verilog projects // Verilog code for RISC Processor // Verilog code for register filemodule GPRs( input clk, // write port input reg_write_en, input [2:0] reg_write_dest, input [15:0] reg_write_data, //read port 1 input [2:0] reg_read_addr_1, output [15:0] reg_read_data_1, //read port 2 input [2:0] reg_read_addr_2, output [15:0] reg_read_data_2); reg [15:0] reg_array [7:0]; integer i; // write port //reg [2:0] i; initial begin for(i=0;i<8;i=i 1) reg_array[i] <= 16'd0; end always @ (posedge clk ) begin if(reg_write_en) begin reg_array[reg_write_dest] <= reg_write_data; end end assign reg_read_data_1 = reg_array[reg_read_addr_1]; assign reg_read_data_2 = reg_array[reg_read_addr_2];
endmodule3. Verilog code for Data Memory:
`include "Parameter.v"// fpga4student.com // FPGA projects, VHDL projects, Verilog projects // Verilog code for RISC Processor // Verilog code for data Memorymodule Data_Memory( input clk, // address input, shared by read and write port input [15:0] mem_access_addr, // write port input [15:0] mem_write_data, input mem_write_en, input mem_read, // read port output [15:0] mem_read_data);
reg [`col - 1:0] memory [`row_d - 1:0];integer f;wire [2:0] ram_addr=mem_access_addr[2:0];initial begin $readmemb("./test/test.data", memory); f = $fopen(`filename); $fmonitor(f, "time = %d\n", $time, "\tmemory[0] = %b\n", memory[0], "\tmemory[1] = %b\n", memory[1], "\tmemory[2] = %b\n", memory[2], "\tmemory[3] = %b\n", memory[3], "\tmemory[4] = %b\n", memory[4], "\tmemory[5] = %b\n", memory[5], "\tmemory[6] = %b\n", memory[6], "\tmemory[7] = %b\n", memory[7]); `simulation_time; $fclose(f); end always @(posedge clk) begin if (mem_write_en) memory[ram_addr] <= mem_write_data; end assign mem_read_data = (mem_read==1'b1) ? memory[ram_addr]: 16'd0;
endmodule4. Verilog code for ALU unit:
// fpga4student.com // FPGA projects, VHDL projects, Verilog projects // Verilog code for RISC Processor // Verilog code for ALUmodule ALU( input [15:0] a, //src1 input [15:0] b, //src2 input [2:0] alu_control, //function sel output reg [15:0] result, //result output zero );
always @(*)begin case(alu_control) 3'b000: result = a b; // add 3'b001: result = a - b; // sub 3'b010: result = ~a; 3'b011: result = a< 3'b100: result = a>>b; 3'b101: result = a 
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