基于LatticeXP2设计的FPGA标准评估技术

LatticeXP2器件包括基于查找表（LUT）的 FPGA以及非易失闪存单元（flexiFLASH）。LatticeXP2系列器件的LUT从5K到40K，分布是RAM从10K到83Kb，EBR SRAM从166Kb到885Kb，EBR SRAM区块从9到48个，sysDSP从3个到8个，18x18乘法器从12个到32个，可用的I/O从172个到540个，GPLL从2个到4个。工作电压1.2V，主要用在对成本敏感的市场如消费类电子，汽车电子，医疗和工业，网络和计算。

LatticeXP2主要特性：



LatticeXP2系列产品：


图1。LatticeXP2-17器件简化方框图（顶视图）

LatticeXP2 devices are ideal for a variety of applications in cost sensitive markets such as Consumer, Automotive, Medical & Industrial, Networking and Computing

LatticeXP2标准评估板

LatticeXP2 Standard Evaluation Board

The LatticeXP2™ Standard Evaluation Board provides a convenient platform to evaluate, test and debug user designs. The board features a LatticeXP2-17 FPGA in a 484 fpBGA package. The LatticeXP2 I/Os are connected to a rich variety of interfaces described later in this document.

This document (including the schematics in the appendix) describes LatticeXP2 Standard Evaluation Boards marked as Rev 000. This marking can be seen on the etching on the back of the printed circuit board, under the Lattice Semiconductor logo.

The LatticeXP2 is a third-generation non-volatile FPGA device. It combines a Look-up Table (LUT) based FPGA fabric with Flash Non-volatile cells in a flexiFLASH™ architecture. The flexiFLASH approach provides benefits such as instant-on, small footprint, on chip storage with FlashBAK™ embedded block memories and Serial TAG memory and design security. The LatticeXP2 also supports live updates with TransFR™, 128-bit AES Encryption and Dual-Boot technologies. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP™ blocks.

图2。LatticeXP2标准评估板外形图

LatticeXP2标准评估板主要特性：

LatticeXP2 Standard Evaluation Board featuring

LatticeXP2-17 FPGA in 484fpBGA package (LFXP2-17E-6F484C)

On-board Asynch SRAM memory (256Kx32 providing 1Mbyte)

A/D converter (Burr Brown ADS7842)

D/A converter (Burr Brown DAC7617)

10K digital POT

RS232 DB9 "female" connector

Compact Flash connector

8-bit switch

8 general purpose LEDs

4 push-button switches

7-segment LED

Built-in USB download capability (includes MachXO device)

Selectable I/O voltage

SMA connectors for clock and general purpose I/O

PAC607 power manager

on-board oscillator (dip socket)

Proto/test area

SPI flash memory for alternate configuration

Power via Bellnix DC power control modules

LCD connector

图3。LatticeXP2标准评估板电路图（1）

图4。LatticeXP2标准评估板电路图（2）：电源和配置[!--empirenews.page--]

图5。LatticeXP2标准评估板电路图（3）：Bank 0-3

图6。LatticeXP2标准评估板电路图（4）：Bank 4-7

图7。LatticeXP2标准评估板电路图（5）：可编程接口

图8。LatticeXP2标准评估板电路图（6）：旁路电容

图9。LatticeXP2标准评估板电路图（7）：外设和时钟输入

图10。LatticeXP2标准评估板电路图（8）：D/A，A/D，7段和RS232

图11。LatticeXP2标准评估板电路图（9）：紧凑闪存，LVDS，开关和LCD

图12。LatticeXP2标准评估板电路图（10）：异步SRAM

图13。LatticeXP2标准评估板电路图（11）：原型栅格[!--empirenews.page--]

图14。LatticeXP2标准评估板电路图（12）：电源管理

图15。LatticeXP2标准评估板电路图（13）：1.2V和电源

图16。LatticeXP2标准评估板电路图（14）：3.3V电源转换器

图17。LatticeXP2标准评估板电路图（15）：可调整电源

图18。LatticeXP2标准评估板电路图（16）：USB下载PHY

图19。LatticeXP2标准评估板电路图（17）：MachXO电源

图20。LatticeXP2标准评估板电路图（18）：MachXO Bank 0-3

图21。LatticeXP2标准评估板电路图（19）：MachXO Bank 4-7

图22。LatticeXP2标准评估板电路图（20）：布置方案